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FEATURES
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LTC1864/LTC1865 Power, 16-Bit, 250ksps 1- and 2-Channel ADCs in MSOP DESCRIPTION
The LTC(R)1864/LTC1865 are 16-bit A/D converters that are offered in MSOP and SO-8 packages and operate on a single 5V supply. At 250ksps, the supply current is only 850A. The supply current drops at lower speeds because the LTC1864/LTC1865 automatically power down between conversions. These 16-bit switched capacitor successive approximation ADCs include sample-andholds. The LTC1864 has a differential analog input with an adjustable reference pin. The LTC1865 offers a softwareselectable 2-channel MUX and an adjustable reference pin on the MSOP version. The 3-wire, serial I/O, small MSOP or SO-8 package and extremely high sample rate-to-power ratio make these ADCs ideal choices for compact, low power, high speed systems. These ADCs can be used in ratiometric applications or with external references. The high impedance analog inputs and the ability to operate with reduced spans down to 1V full scale, allow direct connection to signal sources in many applications, eliminating the need for external gain stages.
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16-Bit 250ksps ADCs in MSOP Package Single 5V Supply Low Supply Current: 850A (Typ) Auto Shutdown Reduces Supply Current to 2A at 1ksps True Differential Inputs 1-Channel (LTC1864) or 2-Channel (LTC1865) Versions SPI/MICROWIRETM Compatible Serial I/O 16-Bit Upgrade to 12-Bit LTC1286/LTC1298 Pin Compatible with 12-Bit LTC1860/LTC1861 Guaranteed Operation to +125C (MSOP Package)
APPLICATIONS
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High Speed Data Acquisition Portable or Compact Instrumentation Low Power Battery-Operated Instrumentation Isolated and/or Remote Data Acquisition
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
Single 5V Supply, 250ksps, 16-Bit Sampling ADC
1F 5V SUPPLY CURRENT (A) 100
Supply Current vs Sampling Frequency
1000
LTC1864 1 2 ANALOG INPUT 0V TO 5V 3 4 VREF IN+ IN- GND VCC SCK SDO CONV 8 7 6 5
18645 TA01
10
1
SERIAL DATA LINK TO ASIC, PLD, MPU, DSP OR SHIFT REGISTERS
0.1
0.01 0.01
0.1 10 100 1 SAMPLING FREQUENCY (kHz)
1000
18645 TA02
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LTC1864/LTC1865 ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltage (VCC) .................................................7V Ground Voltage Difference AGND, DGND LTC1865 MSOP Package ............ 0.3V Analog Input ................ (GND - 0.3V) to (VCC + 0.3V) Digital Input ................................ (GND - 0.3V) to 7V Digital Output .............. (GND - 0.3V) to (VCC + 0.3V) Power Dissipation .............................................. 400mW
Operating Temperature Range LTC1864C/LTC1865C/ LTC1864AC/LTC1865AC...........................0C to 70C LTC1864I/LTC1865I/ LTC1864AI/LTC1865AI ...................... - 40C to 85C LTC1864H/LTC1865H LTC1864AH/LTC1865AH ................. - 40C to 125C Storage Temperature Range...................-65C to 150C Lead Temperature (Soldering, 10 sec) ..................300C
PIN CONFIGURATION
LTC1864
VREF IN+ IN GND 1 2 3 4 TOP VIEW 8 7 6 5 VCC SCK SDO CONV
LTC1865
CONV CH0 CH1 AGND DGND 1 2 3 4 5
TOP VIEW 10 9 8 7 6 VREF VCC SCK SDO SDI
MS8 PACKAGE 8-LEAD PLASTIC MSOP TJMAX = 150C, JA = 210C/W
MS PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 150C, JA = 210C/W
LTC1864
VREF 1 IN+ IN- 2 3
TOP VIEW 8 VCC 7 SCK 6 SDO 5 CONV
LTC1865
CONV 1 CH0 2 CH1 3 GND 4
TOP VIEW 8 VCC 7 SCK 6 SDO 5 SDI
GND 4
S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 150C, JA = 175C/W
S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 150C, JA = 175C/W
ORDER INFORMATION
LEAD FREE FINISH LTC1864CMS8#PBF LTC1864IMS8#PBF LTC1864HMS8#PBF LTC1864ACMS8#PBF LTC1864AIMS8#PBF LTC1864AHMS8#PBF LTC1864CS8#PBF LTC1864IS8#PBF LTC1864ACS8#PBF LTC1684AIS8#PBF LTC1865CMS#PBF LTC1865IMS#PBF TAPE AND REEL LTC1864CMS8#TRPBF LTC1864IMS8#TRPBF LTC1864HMS8#TRPBF LTC1864ACMS8#TRPBF LTC1864AIMS8#TRPBF LTC1864AHMS8#TRPBF LTC1864CS8#TRPBF LTC1864IS8#TRPBF LTC1864ACS8#TRPBF LTC1684AIS8#TRPBF LTC1865CMS#TRPBF LTC1865IMS#TRPBF PART MARKING LTHQ LTHQ LTHQ LTHQ LTHQ LTHQ 1864 1864I 1864A 1864AI LTHS LTHS PACKAGE DESCRIPTION 8-Lead Plastic MSOP 8-Lead Plastic MSOP 8-Lead Plastic MSOP 8-Lead Plastic MSOP 8-Lead Plastic MSOP 8-Lead Plastic MSOP 8-Lead Plastic SO 8-Lead Plastic SO 8-Lead Plastic SO 8-Lead Plastic SO 10-Lead Plastic MSOP 10-Lead Plastic MSOP TEMPERATURE RANGE 0C to 70C -40C to 85C -40C to 125C 0C to 70C -40C to 85C -40C to 125C 0C to 70C -40C to 85C 0C to 70C -40C to 85C 0C to 70C -40C to 85C
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LTC1864/LTC1865 ORDER INFORMATION
LEAD FREE FINISH LTC1865HMS#PBF LTC1865ACMS#PBF LTC1865AIMS#PBF LTC1865AHMS#PBF LTC1865CS8#PBF LTC1865IS8#PBF LTC1865ACS8#PBF LTC1865AIS8#PBF LEAD BASED FINISH LTC1864CMS8 LTC1864IMS8 LTC1864HMS8 LTC1864ACMS8 LTC1864AIMS8 LTC1864AHMS8 LTC1864CS8 LTC1864IS8 LTC1864ACS8 LTC1684AIS8 LTC1865CMS LTC1865IMS LTC1865HMS LTC1865ACMS LTC1865AIMS LTC1865AHMS LTC1865CS8 LTC1865IS8 LTC1865ACS8 LTC1865AIS8 TAPE AND REEL LTC1865HMS#TRPBF LTC1865ACMS#TRPBF LTC1865AIMS#TRPBF LTC1865AHMS#TRPBF LTC1865CS8#TRPBF LTC1865IS8#TRPBF LTC1865ACS8#TRPBF LTC1865AIS8#TRPBF TAPE AND REEL LTC1864CMS8#TR LTC1864IMS8#TR LTC1864HMS8#TR LTC1864ACMS8#TR LTC1864AIMS8#TR LTC1864AHMS8#TR LTC1864CS8#TR LTC1864IS8#TR LTC1864ACS8#TR LTC1684AIS8#TR LTC1865CMS#TR LTC1865IMS#TR LTC1865HMS#TR LTC1865ACMS#TR LTC1865AIMS#TR LTC1865AHMS#TR LTC1865CS8#TR LTC1865IS8#TR LTC1865ACS8#TR LTC1865AIS8#TR PART MARKING LTHS LTHS LTHS LTHS 1865 1865I 1865A 1865AI PART MARKING LTHQ LTHQ LTHQ LTHQ LTHQ LTHQ 1864 1864I 1864A 1864AI LTHS LTHS LTHS LTHS LTHS LTHS 1865 1865I 1865A 1865AI PACKAGE DESCRIPTION 10-Lead Plastic MSOP 10-Lead Plastic MSOP 10-Lead Plastic MSOP 10-Lead Plastic MSOP 8-Lead Plastic SO 8-Lead Plastic SO 8-Lead Plastic SO 8-Lead Plastic SO PACKAGE DESCRIPTION 8-Lead Plastic MSOP 8-Lead Plastic MSOP 8-Lead Plastic MSOP 8-Lead Plastic MSOP 8-Lead Plastic MSOP 8-Lead Plastic MSOP 8-Lead Plastic SO 8-Lead Plastic SO 8-Lead Plastic SO 8-Lead Plastic SO 10-Lead Plastic MSOP 10-Lead Plastic MSOP 10-Lead Plastic MSOP 10-Lead Plastic MSOP 10-Lead Plastic MSOP 10-Lead Plastic MSOP 8-Lead Plastic SO 8-Lead Plastic SO 8-Lead Plastic SO 8-Lead Plastic SO TEMPERATURE RANGE -40C to 125C 0C to 70C -40C to 85C -40C to 125C 0C to 70C -40C to 85C 0C to 70C -40C to 85C TEMPERATURE RANGE 0C to 70C -40C to 85C -40C to 125C 0C to 70C -40C to 85C -40C to 125C 0C to 70C -40C to 85C 0C to 70C -40C to 85C 0C to 70C -40C to 85C -40C to 125C 0C to 70C -40C to 85C -40C to 125C 0C to 70C -40C to 85C 0C to 70C -40C to 85C
Consult LTC Marketing for parts specified with wider operating temperature ranges. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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LTC1864/LTC1865 CONVERTER AND MULTIPILEXER CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 5V, VREF = 5V, fSCK = fSCK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted.
LTC1864/LTC1865 PARAMETER Resolution No Missing Codes Resolution INL Transition Noise Gain Error Offset Error LTC1864 SO-8 and MSOP LTC1865 MSOP , LTC1865 SO-8 IN+ Input IN- Input LTC1864 SO-8 and MSOP , LTC1865 MSOP (Note 4) In Sample Mode During Conversion
l l l l l
LTC1864A/LTC1865A MIN 16 15 TYP MAX UNITS Bits Bits 6 6.5 1.1 20 2 3 0 -0.05 -0.05 1 5 7 VREF VCC + 0.05 VCC/2 VCC 1 12 5 LSB LSB LSBRMS mV mV mV V V V V A pF pF
CONDITIONS
l l l l
MIN 16 14
TYP
MAX
(Note 3) H-Grade (Note 3)
8 8.5 1.1 20 2 3 0 -0.05 -0.05 1 5 7 VREF VCC + 0.05 VCC/2 VCC 1 12 5
Input Differential Voltage Range VIN = IN+ - IN- Absolute Input Range VREF Input Range Analog Input Leakage Current CIN Input Capacitance
DYNAMIC ACCURACY
TA = 25C. VCC = 5V, VREF = 5V, fSAMPLE = 250kHz, unless otherwise noted.
LTC1864/LTC1865 SYMBOL SNR S/(N + D) THD PARAMETER Signal-to-Noise Ratio Signal-to-Noise Plus Distortion Ratio Total Harmonic Distortion Up to 5th Harmonic Full Power Bandwidth Full Linear Bandwidth S/(N+D) 75dB 10kHz Input Signal 100kHz Input Signal 10kHz Input Signal 100kHz Input Signal CONDITIONS MIN TYP 87 83 76 88 77 20 125 MAX UNITS dB dB dB dB dB MHz kHz
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LTC1864/LTC1865 DIGITAL AND DC ELECTRICAL CHARACTERISTICS
SYMBOL VIH VIL IIH IIL VOH VOL IOZ ISOURCE ISINK IREF ICC PARAMETER High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High Level Output Voltage Low Level Output Voltage Hi-Z Output Leakage Output Source Current Output Sink Current Reference Current (LTC1864 SO-8 and MSOP , LTC1865 MSOP) Supply Current CONDITIONS VCC = 5.25V VCC = 4.75V VIN = VCC VIN = 0V VCC = 4.75V, IO = 10A VCC = 4.75V, IO = 360A VCC = 4.75V, IO = 1.6mA CONV = VCC VOUT = 0V VOUT = VCC CONV = VCC fSMPL = fSMPL(MAX) CONV = VCC After Conversion CONV = VCC After Conversion, H-Grade fSMPL = fSMPL(MAX) fSMPL = fSMPL(MAX)
l l l l l l
The denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. VCC = 5V, VREF = 5V, unless otherwise noted.
LTC1864/LTC1865 MIN 2.4 0.8 2.5 -2.5 4.5 2.4 4.74 4.72 0.4 3 -25 20 0.001 0.05 0.001 0.001 0.85 4.25 3 0.1 3 5 1.3 TYP MAX UNITS V V A A V V V A mA mA A mA A A mA mW
PD
Power Dissipation
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LTC1864/LTC1865 RECOMMENDED OPERATING CONDITIONS
full operating temperature range, otherwise specifications are TA = 25C.
LTC1864/LTC1865 SYMBOL VCC fSCK tCYC tSMPL tsuCONV thDI tsuDI tWHCLK tWLCLK tWHCONV tWLCONV thCONV PARAMETER Supply Voltage Clock Frequency H-Grade Total Cycle Time Analog Input Sampling Time Setup Time CONV Before First SCK (See Figure 1) Hold Time SDI After SCK Setup Time SSDI Stable Before SCK SCK High Time SCK Low Time CONV High Time Between Data Transfer Cycles CONV Low Time During Data Transfer Hold Time CONV Low After Last SCK LTC1864 (Note 5) LTC1865 (Note 5) H-Grade LTC1865 LTC1865 fSCK = fSCK(MAX) fSCK = fSCK(MAX) (Note 5) (Note 5)

The denotes specifications which apply over the
CONDITIONS
MIN 4.75
TYP
MAX 5.25 20 16.7
UNITS V MHz MHz s SCK SCK
16 * SCK + tCONV 16 14 60 65 15 15 40% 40% tCONV 16 13 30 30
ns ns ns ns 1/fSCK 1/fSCK s SCK ns
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LTC1864/LTC1865 TIMING CHARACTERISTICS
SYMBOL tCONV fSMPL(MAX) tdDO PARAMETER Conversion Time (See Figure 1) H-Grade Maximum Sampling Frequency H-Grade Delay Time, SCK to SDO Data Valid CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF H-Grade , H-Grade ten thDO tr tf Delay Time, CONV to SDO Enabled CLOAD = 20pF CLOAD = 20pF H-Grade , CLOAD = 20pF CLOAD = 20pF
The denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. VCC = 5V, VREF = 5V, fSCK = fSCK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted.
LTC1864/LTC1865 CONDITIONS

MIN
TYP 2.75 2.75
MAX 3.2 3.3
UNITS s s kHz kHz
250 234 15 20 25 30 60 65 60 65
ns ns ns ns ns ns ns ns ns ns
tdis
Delay Time, CONV to SDO Hi-Z
30 30 30 30 5 10 8 4
Time Output Data Remains Valid After SCK CLOAD = 20pF SDO Rise Time SDO Fall Time
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND.
Note 3: Integral nonlinearity is defined as deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 4: Channel leakage current is measured while the part is in sample mode. Note 5: Guaranteed by design, not subject to test.
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LTC1864/LTC1865 TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs Sampling Frequency
1000 VCC = 5V TA = 25C CONV LOW = 800ns 1000
Supply Current vs Temperature
1000 900 800 SUPPLY CURRENT (A) SLEEP CURRENT (nA) 800 700 600 500 400 300 200 100
Sleep Current vs Temperature
CONV = VCC = 5V
100 SUPPLY CURRENT (A)
10
600
1
400 VCC = 5V VREF = 5V fSAMPLE = 250kHz CONV HIGH = 3.2S -25 50 25 0 75 TEMPERATURE (C) 100 125
0.1
200
0.01 0.01
0.1 10 100 1.0 SAMPLING FREQUENCY (kHz)
1000
18645 G01
0 -50
0 -50
-25
50 25 0 75 TEMPERATURE (C)
100
125
18645 G02
18645 G03
Reference Current vs Sampling Rate
60 50 REFERENCE CURRENT (A) 40 30 20 10 0 VCC = 5V TA = 25C VREF = 5V CONV LOW = 800ns 55
Reference Current vs Temperature
VCC = 5V 54 VREF = 5V f = 250kHz 53 S 52 51 50 49 48 47 46 60 50 REFERENCE CURRENT (A) 40 30 20 10 0 -25 50 25 0 75 TEMPERATURE (C) 100 125
Reference Current vs Reference Voltage
VCC = 5V TA = 25C fS = 250kHz
REFERENCE CURRENT (A)
0
50
100 150 200 SAMPLE RATE (kHz)
250
18645 G04
45 -50
0
1
2
3 VREF (V)
4
5
18645 G06
18645 G05
Typical INL Curve
4 VCC = 5V TA = 25C VREF = 5V 2 DNL ERROR (LSBs) INL ERROR (LSBs) 1 2
Typical DNL Curve
VCC = 5V TA = 25C VREF = 5V 100
Analog Input Leakage Current vs Temperature
VCC = 5V VREF = 5V CONV = 0V
ANALOG INPUT LEAKAGE (nA) 32768 CODE 65536
18645 G08
75
0
0
50
-2
-1
25
-4
0
16384
32768 CODE
49152
65536
18645 G07
-2
0
16384
49152
0 -50
-25
0
25
50
75
100
125
TEMPERATURE (C)
18645 G09
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LTC1864/LTC1865 TYPICAL PERFORMANCE CHARACTERISTICS
Change in Offset Error vs Reference Voltage
75 CHANGE IN OFFSET ERROR (LSB) VCC = 5V TA = 25C CHANGE IN OFFSET (LSB) 5
Change in Offset vs Temperature
20 VCC = 5V 4 VREF = 5V 3 2 1 0 -1 -2 -3 -4 CHANGE IN GAIN ERROR (LSB)
Change in Gain Error vs Reference Voltage
VCC = 5V 15 TA = 25C 10 5 0 -5 -10 -15 -20
50
25
0
-25
0
1
3 4 2 REFERENCE VOLTAGE (V)
5
18645 G10
-5 -50
-25
50 25 0 75 TEMPERATURE (C)
100
125
0
1
4 3 2 REFERENCE VOLTAGE(V)
5
18645 G12
18645 G11
Change in Gain Error vs Temperature
5 4 CHANGE IN GAIN ERROR (LSB) 3 2 1 0 -1 -2 -3 -4 -5 -50 -25 50 25 0 75 TEMPERATURE (C) 100 125 FREQUENCY VCC = 5V VREF = 5V 1800 1600 1400 1200 1000 800 600 400 200 0
Histogram of 4096 Conversions of a DC Input Voltage
1534 VCC = 5V TA = 25C VREF = 5V AMPLITUDE (dB) 0 -20 -40 -60 -80
4096 Point FFT Nonaveraged
fS = 203.125kHz fIN = 99.72763kHz VCC = 5V VREF = 5V TA = 25C
1178
729 516
-100 -120 12 0 4 0 5
18645 G14
127 0 0 0 1 CODE 2 -4 -3 -2 -1 3
-140 0 20 40 60 80 FREQUENCY (kHz) 100 120
18645 G13
18645 G15
SINAD vs Frequency
100 90 80 70 SINAD (dB) 60 50 40 30 20 10 0 1 10 FIN (kHz)
18645 G16
THD vs Frequency
0 SNR -10 -20 SINAD THD (dB) -30 SFDR (dB) VCC = 5V VREF = 5V TA = 25C VIN = 0dB 1 10 FIN (kHz)
18645 G17
SFDR vs Frequency
100 90 80 70 60 50 40 30 20 10 0 1 10 FIN (kHz)
18645 G18
-40 -50 -60 -70
VCC = 5V VREF = 5V TA = 25C VIN = 0dB 100 1000
-80 -90 -100 100
VCC = 5V VREF = 5V TA = 25C VIN = 0dB 100 1000
1000
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LTC1864/LTC1865 PIN FUNCTIONS
LTC1864 VREF (Pin 1): Reference Input. The reference input defines the span of the A/D converter and must be kept free of noise with respect to GND. (Pins 2, 3): Analog Inputs. These inputs must be free of noise with respect to GND. GND (Pin 4): Analog Ground. GND should be tied directly to an analog ground plane. CONV (Pin 5): Convert Input. A logic high on this input starts the A/D conversion process. If the CONV input is left high after the A/D conversion is finished, the part LTC1865 (MSOP Package) CONV (Pin 1): Convert Input. A logic high on this input starts the A/D conversion process. If the CONV input is left high after the A/D conversion is finished, the part powers down. A logic low on this input enables the SDO pin, allowing the data to be shifted out. CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must be free of noise with respect to AGND. AGND (Pin 4): Analog Ground. AGND should be tied directly to an analog ground plane. DGND (Pin 5): Digital Ground. DGND should be tied directly to an analog ground plane. SDI (Pin 6): Digital Data Input. The A/D configuration word is shifted into this input. LTC1865 (SO-8 Package) CONV (Pin 1): Convert Input. A logic high on this input starts the A/D conversion process. If the CONV input is left high after the A/D conversion is finished, the part powers down. A logic low on this input enables the SDO pin, allowing the data to be shifted out. CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must be free of noise with respect to GND. GND (Pin 4): Analog Ground. GND should be tied directly to an analog ground plane. SDI (Pin 5): Digital Data Input. The A/D configuration word is shifted into this input. SDO (Pin 6): Digital Data Output. The A/D conversion result is shifted out of this output. SCK (Pin 7): Shift Clock Input. This clock synchronizes the serial data transfer. VCC (Pin 8): Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. VREF is tied internally to this pin. SDO (Pin 7): Digital Data Output. The A/D conversion result is shifted out of this output. SCK (Pin 8): Shift Clock Input. This clock synchronizes the serial data transfer. VCC (Pin 9): Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. VREF (Pin 10): Reference Input. The reference input defines the span of the A/D converter and must be kept free of noise with respect to AGND. IN +, IN- powers down. A logic low on this input enables the SDO pin, allowing the data to be shifted out. SDO (Pin 6): Digital Data Output. The A/D conversion result is shifted out of this pin. SCK (Pin 7): Shift Clock Input. This clock synchronizes the serial data transfer. VCC (Pin 8): Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane.
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LTC1864/LTC1865 FUNCTIONAL BLOCK DIAGRAM
VCC PIN NAMES IN PARENTHESES REFER TO LTC1865 CONV (SDI) SCK
CONVERT CLK
BIAS AND SHUTDOWN DATA IN
SERIAL PORT
SDO
16 BITS IN+ (CH0) IN- (CH1)
+ -
16-BIT SAMPLING ADC
DATA OUT
18645 BD
GND
VREF
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LTC1864/LTC1865 TEST CIRCUITS
Load Circuit for tdDO, tr, tf, tdis and ten
TEST POINT SDO 3k SDO 20pF tdis WAVEFORM 1
18645 TC01
Voltage Waveforms for SDO Rise and Fall Times, tr, tf
VOH VOL
VCC tdis WAVEFORM 2, ten tr tf
18645 TC04
Voltage Waveforms for ten
CONV CONV
18645 TC03
Voltage Waveforms for tdis
VIH
SDO ten
SDO WAVEFORM 1 (SEE NOTE 1) tdis SDO WAVEFORM 2 (SEE NOTE 2)
90%
Voltage Waveforms for SDO Delay Times,tdDO and thDO
SCK VIL tdDO thDO VOH SDO VOL
18645 TC02
10%
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL
18645 TC05
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LTC1864/LTC1865 APPLICATIONS INFORMATION
LTC1864 OPERATION Operating Sequence The LTC1864 conversion cycle begins with the rising edge of CONV. After a period equal to t CONV, the conversion is finished. If CONV is left high after this time, the LTC1864 goes into sleep mode drawing only leakage current. On the falling edge of CONV, the LTC1864 goes into sample mode and SDO is enabled. SCK synchronizes the data transfer with each bit being transmitted from SDO on the falling SCK edge. The receiving system should capture the data from SDO on the rising edge of SCK. After completing the data transfer, if further SCK clocks are applied with CONV low, SDO will output zeros indefinitely. See Figure 1. Analog Inputs The LTC1864 has a unipolar differential analog input. The converter will measure the voltage between the "IN + " and "IN-" inputs. A zero code will occur when IN+ minus IN- equals zero. Full scale occurs when IN+ minus IN- equals VREF minus 1LSB. See Figure 2. Both the "IN+" and "IN-" inputs are sampled at the same time, so common mode noise on the inputs is rejected by the ADC. If "IN-" is grounded and VREF is tied to VCC, a rail-to-rail input span will result on "IN+" as shown in Figure 3. Reference Input The voltage on the reference input of the LTC1864 defines the full-scale range of the A/D converter. The LTC1864 can operate with reference voltages from VCC to 1V.
tsuCONV CONV tCONV SLEEP MODE 1 SCK 2 3 4 5 6 7 tSMPL 8 9 10 11 12 13 14 15 16
SDO Hi-Z
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0*
Hi-Z
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY
18645 F01
Figure 1. LTC1864 Operating Sequence
1111111111111111 1111111111111110
1F VCC
* * *
0000000000000001 0000000000000000 0V 1LSB VREF VREF - 1LSB VREF - 2LSB *VIN = IN+ - IN- VIN* VIN = 0V TO VCC 1 2 3 4
18645 F02
LTC1864 VREF IN+ IN- GND VCC SCK SDO CONV 8 7 6 5
18645 F03
SERIAL DATA LINK TO ASIC, PLD, MPU, DSP OR SHIFT REGISTERS
Figure 2. LTC1864 Transfer Curve
Figure 3. LTC1864 with Rail-to-Rail Input Span
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LTC1864/LTC1865 APPLICATIONS INFORMATION
LTC1865 OPERATION Operating Sequence The LTC1865 conversion cycle begins with the rising edge of CONV. After a period equal to t CONV, the conversion is finished. If CONV is left high after this time, the LTC1865 goes into sleep mode drawing only leakage current. The LTC1865's 2-bit data word is clocked into the SDI input on the rising edge of SCK after CONV goes low. Additional inputs on the SDI pin are then ignored until the next CONV cycle. The shift clock (SCK) synchronizes the data transfer with each bit being transmitted on the falling SCK edge and captured on the rising SCK edge in both transmitting and receiving systems. The data is transmitted and received simultaneously (full duplex). After completing the data transfer, if further SCK clocks are applied with CONV low, SDO will output zeros indefinitely. See Figure 4. Analog Inputs The two bits of the input word (SDI) assign the MUX configuration for the next requested conversion. For a given channel selection, the converter will measure the voltage between the two channels indicated by the "+" and "-" signs in the selected row of the following table. In single-ended mode, all input channels are measured with respect to GND. A zero code will occur when the "+" input minus the "-" input equals zero. Full scale occurs when the "+" input minus the "-" input equals VREF minus 1LSB. See Figure 5. Both the "+" and "-" inputs are sampled at the same time so common mode noise is rejected. The input span in the SO-8 package is fixed at VREF = VCC. If the "-" input in differential mode is grounded, a rail-to-rail input span will result on the "+" input. Reference Input The reference input of the LTC1865 SO-8 package is internally tied to VCC. The span of the A/D converter is therefore equal to VCC. The voltage on the reference input of the LTC1865 MSOP package defines the span of the A/D converter. The LTC1865 MSOP package can operate with reference voltages from 1V to VCC.
Table 1. Multiplexer Channel Selection
MUX ADDRESS SGL/DIFF ODD/SIGN 0 1 1 1 0 0 1 0 CHANNEL # 0 1 + + + - - + GND - -
SINGLE-ENDED MUX MODE DIFFERENTIAL MUX MODE
18645 TBL1
CONV tCONV
SLEEP MODE
tSMPL
SDI
DON'T CARE
S/D O/S 1 2 3 4 5 6 7
DON'T CARE 8 9 10 11 12 13 14 15 16
SCK
SDO
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0* Hi-Z *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY
Hi-Z
18645 F04
Figure 4. LTC1865 Operating Sequence
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14
LTC1864/LTC1865 APPLICATIONS INFORMATION
GENERAL ANALOG CONSIDERATIONS Grounding The LTC1864/LTC1865 should be used with an analog ground plane and single point grounding techniques. Do not use wire wrapping techniques to breadboard and evaluate the device. To achieve the optimum performance, use a printed circuit board. The ground pins (AGND and DGND for the LTC1865 MSOP package and GND for the LTC1864 and LTC1865 SO-8 package) should be tied directly to the analog ground plane with minimum lead length. Bypassing For good performance, the VCC and VREF pins must be free of noise and ripple. Any changes in the VCC/VREF voltage with respect to ground during the conversion cycle can induce errors or noise in the output code. Bypass the VCC and VREF pins directly to the analog ground plane with a minimum of 1F tantalum. Keep the bypass capacitor leads as short as possible. Analog Inputs Because of the capacitive redistribution A/D conversion techniques used, the analog inputs of the LTC1864/LTC1865 have capacitive switching input current spikes. These current spikes settle quickly and do not cause a problem if source resistances are less than 200 or high speed op amps are used (e.g., the LT(R)1211, LT1469, LT1807, LT1810, LT1630, LT1226 or LT1215). But if large source resistances are used, or if slow settling op amps drive the inputs, take care to ensure the transients caused by the current spikes settle completely before the conversion begins.
1111111111111111 1111111111111110
* * *
0000000000000001 0000000000000000 0V 1LSB VCC VCC - 1LSB VCC - 2LSB VIN*
*VIN = (SELECTED "+" CHANNEL) - (SELECTED "-" CHANNEL) REFER TO TABLE 1
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Figure 5. LTC1865 Transfer Curve
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15
LTC1864/LTC1865
APPLICATIONS INFORMATION
16
LTC1864 Evaluation Circuit Schematic
5VDIG C13 0.1F C14 0.1F J4 3201S40G1 5VDIG 15V 1 VIN C26 10F 6.3V 1206 3 C1 0.1F 5VAN C3 10F 6.3V 1206 C4 0.1F RN1 330 R5 402, 1% C21 47pF U8A 74AC14 2 JP2 C7 390pF C9 180pF R6 402 1% C22 47pF U8B 74AC14 U3 LTC1864CMS8 C8 1000pF OPT 1 2 3 4 8 7 6 5 R1 510 1 V 2 REF IN+ 3 IN- 4 GND 8 VCC 7 SCK 6 SDO 5 CONV C2 1F 10V 0805 VOUT GND 2 R4 2 R3 2 5VAN 5VDIG 2 JP1 U4 5VDIG 74HC595ADT 16 QB V 15 CC QC QA 14 QD A 13 QE OENB 12 QF LCLK 11 QG SCLK 10 RESET QH 9 GND SQH 1 2 3 4 5 6 7 8 R2 510 C11 390pF C12 1000pF OPT C10 680pF OPT
E1
15V
15V
2
VIN
C27 0.1F
6 VOUT U1 GND LT1021-5 4
J1
IN+
IN+
1
R7 51 0PT
C5 15V 0.1F
+
E8
U2 OPT
1
AGND
-
E9
J2
C6 -15V 0.1F
IN-
IN-
R8 51 0PT
2 JP3 1
ANALOG GROUND PLANE
5VDIG C23 0.1F 5VDIG C24 0.1F
16 15 14 13 12 11 10 9
QB VCC QC QA QD A QE OENB QF LCLK QG SCLK RESET QH GND SQH
1 2 3 4 5 6 7 8
39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1
40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 C15 5VDIG 0.1F U5 74HC595ADT U9C 74AC00 U9D 74AC00
U9B 74AC00 2 C25 5VDIG 0.1F
U12A 74AC109 16 6 2 VCC J Q 3 7 K Q 4 CLK 1 CLR 5 8 PRE GND 5VDIG C16 0.1F C17 0.1F 5VDIG 5VDIG U8D 74AC14
U12B 74AC109 16 14 10 VCC JP4 J Q 13 91 K Q 12 CLK 15 CLR 11 8 PRE GND
E2
CONV E3 ENABLE DATA E7 DGND 2 JP5 U8E 74AC14 U8F 74AC14 1 E6 E4 E5 J3 CLKIN 1 C19 5VDIG 0.1F DGND DOUT CLKOUT
U9A 74AC00
5VDIG U7 74HC163AD R12 10k 5VDIG C18 0.1F
5VDIG
2
4
6
U6 74HC163AD
JP8
1
3
5
U10 LTC1799 OUT DIV 5 1+ V 2 GND 3 SET R10 20k 4 3
JP6 2 1
2 3
R9 51 JP7
2
4
6
1 2 3 4 5 6 7 8 VCC RCO Q0 Q1 Q2 Q3 ENT LO 1 2 3 4 5 6 7 8 RESET CLK P0 P1 P2 P3 ENP GND VCC RCO Q0 Q1 Q2 Q3 ENT LO 16 15 14 13 12 11 10 9
JP9
RESET CLK P0 P1 P2 P3 ENP GND
16 15 14 13 12 11 10 9
U8C 74AC14
U13A 74AC32
U13D 74AC32
1
3
5 CLK U13B 74AC32 U13C 74AC32
NOTES: UNLESS OTHERWISE SPECIFIED INSTALL SHUNTS ON JP1, JP3-JP7 PIN 1 AND PIN2; ON JP8 AND JP9 PIN 2 AND PIN 4, PIN 3 AND PIN 5.
18645 AI1
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LTC1864/LTC1865 APPLICATIONS INFORMATION
Component Side Silk Screen for LTC1864 Evaluation Circuit
Component Side Showing Traces (Note Sider Traces on Analog Side)
Bottom Side Showing Traces (Note Almost No Analog Traces on Board Bottom)
Ground Layer with Separate Analog and Digital Grounds
Supply Layer with 5V Digital Supply and Analog Ground Repeated
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17
LTC1864/LTC1865 APPLICATIONS INFORMATION
U11 15V LT1121CST-5 1 VIN VOUT GND 2
5VAN 3
R4 2
5VDIG C26 10F 6.3V 1206
5VAN C3 10F 6.3V 1206 1V to 5V REFERENCE 0V to VREF INPUT C4 0.1F
5VDIG 1 V 2 REF IN+ 3 IN- 4 GND 8 VCC 7 SCK 6 SDO 5 CONV RN1 330 1 2 3 4 8 7 6 5
LTC1485 1 RO 2 RE 3 DE 4 DI 8 VCC 7 B 6 A 5 GND
5VDIG
15V
120
U3 LTC1864CMS8
ANALOG GROUND PLANE
5VDIG C23 0.1F 5VDIG C24 0.1F
4 CONDUCTOR TELEPHONE WIRES TO RECEIVER 4 1 2 500 5 MC74VHC1G66 3
U9B 74AC00
U12A 74AC109 16 6 2 VCC J Q 7 3 K Q 4 CLK 1 CLR 8 5 PRE GND v 5VDIG C16 0.1F 5VDIG 5VDIG C17 0.1F
U12B 74AC109 16 14 10 VCC J Q 13 9 K Q 12 CLK 15 CLR 11 8 PRE GND v
5V
U9A 74AC00
5VDIG 74AC74 74AC86
5VDIG U6 74HC163AD 1 2 3 4 5 6 7 8 RESET CLK P0 P1 P2 P3 ENP GND VCC RCO Q0 Q1 Q2 Q3 ENT LO 16 15 14 13 12 11 10 9
U7 74HC163AD 1 2 3 4 5 6 7 8 RESET CLK P0 P1 P2 P3 ENP GND VCC RCO Q0 Q1 Q2 Q3 ENT LO 16 15 14 13 12 11 10 9
5VDIG
C18 0.1F U10 LTC1799
PRE D CLK CLR 5VDIG
Q
v
Q
100k
1+ V 2 GND 3 SET
OUT DIV
5 4
74AC74 PRE D CLK CLR Q
U13C 74AC32 CLK
v
Q
18645 AI2
U13B 74AC32
Figure 6. LTC1864 Manchester Transmitter
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18
LTC1864/LTC1865 APPLICATIONS INFORMATION
VCC IC5C 74AC86 IC6D 74AC32 IC4A 74AC08 IC2A 74AC74 4 2 CLK 3 1 PRE D CLK CLR Q 5
VCC 10 12 CLK 11 13
IC2B 74AC74 PRE D CLK CLR Q 9
VCC IC4B 74AC08 4 2 CLK 3 1
IC3A 74AC74 PRE D CLK CLR Q 5
VCC 4 DATA IN 2 CLK 3 1
IC1A 74AC74 PRE D CLK CLR Q 5
VCC
v
10 6 12 Q CLK 11 13
PRE D CLK CLR
Q
v
9
Q
6
Q
v
8
Q
6
v
Q
8
IC1B 74AC74
DATA DATA
IC6C 74LS32D
v
IC4D 74AC08
VCC IC4C 74AC08 10 12 CLK 11 13
IC3B 74AC74 PRE D CLK CLR Q9 8 STROBE
v
Q
RECEIVE CLOCK AT 8 X TRANSMIT CLOCK FREQUENCY
IC8 74AC595 14 11 U1 LTC1485 1 RO 2 RE 3 DE 4 DI 8 VCC 7 B 6 A 5 GND OPTIONAL SERIAL TO PARALLEL CONVERTER 15V SUPPLY TO TRANSMITTER VCC VCC 10 12 13 SER SCK SCL RCK v QA QB QC QD QE QF QG QH QHIN 15 1 2 3 4 5 6 7 9 D15 D14 D13 D12 D11 D10 D9 D8
8 IC9 74AC595
VCC 14 11
SER SCK SCL RCK v
STROBE 4 CONDUCTOR TELEPHONE WIRES TO TRANSMITTER IC7B 74AC109 11 14 12 13 15 PRE J CLK K CLR Q 10
10 12 13 Q 9
R1 120
8
DATA
QA QB QC QD QE QF QG QH QHIN
v
15 1 2 3 4 5 6 7 9
D7 D6 D5 D4 D3 D2 D1 D0
18645 AI3
Figure 7. LTC1864 Manchester Receiver
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19
LTC1864/LTC1865 APPLICATIONS INFORMATION
Transmit LTC1864 Data Over Modular Telephone Wire Using Simple Transmitter/Receiver Figure 6 shows a simple Manchester encoder and differential transmitter suitable for use with the LTC1864. This circuit allows transmission of data over inexpensive telephone wire. This is useful for measuring a remote sensor, particularly when the cost of preserving the analog signal over a long distance is high. Manchester encoding is a clock signal that is modulated by exclusive ORing with the data signal. The resulting signal contains both clock and data information and has an average duty cycle of 50%, that also allows transformer coupling. In practice, generating a Manchester encoded signal with an XOR gate will often produce glitches due to the skew between data and clock transitions. The D flip-flops in this encoder retime the clock and data such that the respective edges are closely aligned, effectively suppressing glitches. The retimed data and clock are then XORed to produce the Manchester encoded data, which is interfaced to telephone wire with an LTC1485 RS485 transceiver. In order to synchronize to incoming data, the receiver needs a sequence to indicate the start of a data word. The transmitter schematic shows logic that will produce 31 zeros, a start bit, followed by the 16 data bits (one sample every 48 clock cycles) at a clock frequency of 1MHz set by the LTC1799 oscillator. Sending at least 18 zeros before each start bit ensures that if synchronization is lost, the receiver can resynchronize to a start bit under all conditions. The serial to parallel converter shown in Figure 7 requires 18 zeros to avoid triggering on data bits. The Manchester receiver shown in Figure 7 was adopted from Xilinx application note 17-30 and would typically be implemented in an FPGA. The decoder clock frequency is nominally 8 times the transmit clock frequency and is very tolerant of frequency errors. The outputs of the decoder are data and a strobe that indicates a valid data bit. The data can be deserialized using shift registers as shown. The start bit resets the J-K/flip-flop on its way into the first shift register. When it appears at the QHIN output of the second shift register, it sets the flip-flop that loads the parallel data into the output register. With AC family CMOS logic at 5V the receiver clock frequency is limited to 20MHz; the corresponding transmitter clock frequency is 2.5MHz. If the receiver is implemented in an FPGA that can be clocked at 160MHz, the LTC1864 can be clocked at its rated clock frequency of 20MHz.
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20
LTC1864/LTC1865 PACKAGE DESCRIPTION
MS8 Package 8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
0.889 0.127 (.035 .005)
3.00 0.102 (.118 .004) (NOTE 3)
8
7 65
0.52 (.206) REF
5.23 (.206) MIN
3.2 - 3.45 (.126 - .136)
0.254 (.010) GAUGE PLANE
DETAIL "A" 0 - 6 TYP
4.88 0.1 (.192 .004)
3.00 0.102 (.118 .004) NOTE 4
0.42 0.04 (.0165 .0015) TYP
0.65 (.0256) BSC
1 0.53 0.015 (.021 .006) DETAIL "A" 0.18 (.077) SEATING PLANE 0.22 - 0.38 (.009 - .015) 1.10 (.043) MAX
23
4 0.86 (.034) REF
RECOMMENDED SOLDER PAD LAYOUT
0.65 (.0256) NOTE: BCS 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.13 0.05 (.005 .002)
MSOP (MS8) 1001
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21
LTC1864/LTC1865 PACKAGE DESCRIPTION
MS Package 10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
0.889 0.127 (.035 .005)
3.00 0.102 (.118 .004) (NOTE 3)
10 9 8 7 6
0.497 0.076 (.0196 .003) REF
5.23 (.206) MIN
3.2 - 3.45 (.126 - .136)
0.254 (.010) GAUGE PLANE
DETAIL "A" 0 - 6 TYP
4.88 0.10 (.192 .004)
3.00 0.102 (.118 .004) NOTE 4
0.50 0.305 0.038 (.0197) (.0120 .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT
12345 0.53 0.01 (.021 .006) DETAIL "A" 0.18 (.007) 1.10 (.043) MAX 0.86 (.034) REF
NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
SEATING PLANE
0.17 - 0.27 (.007 - .011)
0.50 (.0197) TYP
0.13 0.05 (.005 .002)
MSOP (MS) 1001
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22
LTC1864/LTC1865 PACKAGE DESCRIPTION
S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
0.189 - 0.197* (4.801 - 5.004) 8 7 6 5
0.228 - 0.244 (5.791 - 6.197)
0.150 - 0.157** (3.810 - 3.988)
SO8 1298
1 0.010 - 0.020 x 45 (0.254 - 0.508) 0.008 - 0.010 (0.203 - 0.254) 0.016 - 0.050 (0.406 - 1.270) 0- 8 TYP
2
3
4
0.053 - 0.069 (1.346 - 1.752)
0.004 - 0.010 (0.101 - 0.254)
0.014 - 0.019 (0.355 - 0.483) TYP *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
0.050 (1.270) BSC
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC1864/LTC1865 TYPICAL APPLICATION
Sample Two Channels Simultaneously with a Single Input ADC
0.1F f1 (0V TO 0.66V) 4.096V REF 28.7k 10k 10k 1F 5k 0.1F f2 (0V TO 2V) 5V 3 0.1F 100 100pF
18645 TA03a
4096 Point FFT of Output
0 10 20 30 40 50 60 70 80 90 100 110 120 130 0 5 f1 = 7.507324kHz AT 530mVP-P f2 = 45.007324kHz AT 1.7VP-P fS = 100kHz
5V
+
1/2 LT1492 5k
100 100pF 20k 5pF 2 8 VCC IN+ IN-
-
0.1F 1 REF 7 SCK 6 LTC1864 SDO 5 CONV GND 4
1F
AMPLITUDE (dB)
4.096V REF
0.1F
1F
+ -
8
10 15 20 25 30 35 40 45 50 FREQUENCY (kHz)
18645 TA03b
1/2 LT1492 4
RELATED PARTS
PART NUMBER 14-Bit Serial I/O ADCs LTC1417 LTC1418 16-Bit Serial I/O ADCs LTC1609 References LT1460 LT1790 Op Amps LT1468/LT1469 LT1806/LT1807 LT1809/LT1810 Single/Dual 90MHz, 16-Bit Accurate Op Amps Single/Dual 325MHz Low Noise Op Amps Single/Dual 180MHz Low Distortion Op Amps 22V/s Slew Rate, 75V/125V Offset 140V/s Slew Rate, 3.5nV/Hz Noise, -80dBc Distortion 350V/s Slew Rate, -90dBc Distortion at 5MHz Micropower Precision Series Reference Micropower Low Dropout Reference Bandgap, 130A Supply Current, 10ppm/C, Available in SOT-23 60A Supply Current, 10ppm/C, SOT-23 200ksps 65mW Configurable Bipolar or Unipolar Input Ranges, 5V 400ksps 200ksps 20mW 15mW 16-Pin SSOP Unipolar or Bipolar, Reference, 5V or 5V , Serial/Parallel I/O, Internal Reference, 5V or 5V SAMPLE RATE POWER DISSIPATION DESCRIPTION
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24 Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
LT 1207 REV B * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2007

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